From this example, it can be seen that tier-to-tier alignment plays a critical role in creating a robust multi-tier 3D NAND memory cell. For example the BIOS of a computer will be stored in ROM. 5 illustrates a plan view of an example of a cell region of the memory cell array of the semiconductor memory according to the embodiment. In the following, embodiments will be described with reference to the drawings. Each of the conductors 21A and 21B is, for example, poly-silicon, and the conductors 21A and 21B are made of an identical material, and thus may be integrally formed. 11, the placement of the slit SHE provided in the depth direction of the cross-sectional view is illustrated by a dashed line. In the following, a description will be made of an example of a structure of the semiconductor memory 1 according to the embodiment. The conductor 22 is provided on the conductor 21B via an insulating layer. The conductor 45 is used as, for example, a micro-pad. FIG. The conductor 23 covers a side surface of the block insulating film 35. FIG. Each provides distinct advantages. 14 illustrates a plan view of an example of the vicinity of the plane separation region of the semiconductor memory according to the embodiment. Thus, the replacement member 62 between the vertical-direction slit SLT in the memory cell array 10A and the vertical-direction slit SLT in the memory cell array 10B is replaced with the conductor 23, and thus the W region corresponding to the memory cell array 10A and the W region corresponding to the memory cell array 10B are continuously formed. The conductor 45 is electrically connected to the corresponding conductor 42 via the contact V2. 11, the slit SHE in the active block ABLK is provided to separate the plurality of conductors 24 respectively corresponding to the select gate lines SGDa, SGDb, and SGDc in the lead region HA. A bottom part of a slit used for the replacement process is formed to be in contact with at least the sacrifice member 62. Structure of Memory Cell Array 10 in Vicinity of Plane Separation Region PNdiv. In other words, the W region provided in each of the planes PN1 and PN2 is, for example, in contact with the region of the dummy steps on one side in the Y direction and is in contact with the BL connection region BLtap on the other side in the Y direction. 3D NAND structures have the added complexity of a “staircase” etch that is required to form the word-line (WL) contacts. Specifically, the vertical-direction slit SLT is provided at one end part of the block group BLKG in the X direction. For that reason, the conductor 64 is preferably provided to protect stacked wirings close to the slit SLT. Figure 1(b) identifies the on-chip location of the minimum contact area. In general, according to an embodiment, a semiconductor memory includes a substrate, and first to fourth stacked bodies. This is only an example, and a region in which the conductor 21B is provided may include at least a region in which the W region is formed in a plan view. In the semiconductor memory 1 according to the embodiment, whether the block BLK provided in the memory cell array 10 is the dummy block DBLK or the active block ABLK may be determined based on whether or not a block address BAd is allocated thereto. In other words, in the active block ABLK, the string unit SU extends in the X direction. The slit SHE contains an insulator such as silicon dioxide (SiO2). In the circuit configuration of the memory cell array 10 described above, drains of the select transistors ST1c corresponding to an identical column among a plurality of blocks BLK are connected to the identical bit line BL. These two types of semiconductor memory have been around for decades. Each of the C4 connection region C4tap of the memory cell array 10A and the C4 connection region C4tap of the memory cell array 10B is in contact with the plane separation region PNdiv. 3 illustrates a plan view of an example of the memory cell array of the semiconductor memory according to the embodiment. 6, a plurality of bit lines BL and a plurality of contacts CH are disposed in the memory cell array 10 in correspondence to the memory pillars MP described with reference to FIG. All rights reserved. 1 illustrates a configuration example of the semiconductor memory 1 according to the embodiment. The core member 30 is covered with the conductor 31. As illustrated in FIG. A side surface and a lower surface of the conductor 31 are covered with the stacked film 32 except for a portion thereof where the conductors 21A and 31 are in contact with each other. For example, dummy steps are formed in the peripheral region. An insulating layer and the conductor 23 are alternately stacked on the conductor 22. In other words, in a plan view, the region in which the conductor 21B includes the region in which the conductor 22 is provided. 4 illustrates a plan view of an example of the memory cell array of the semiconductor memory according to the first embodiment. 14) in the first layer of the fourth region, and a sixth insulator and an eighth conductor alternately stacked on the seventh conductor. In a manufacturing process for a semiconductor memory in which memory cells are stacked in a three-dimensional manner, in a case where a stacked wiring such as the word line WL is formed, first, a stacked body in which a replacement member and an insulating film are alternately stacked is formed. A plurality of horizontal-direction slits SLT arranged in the Y direction are in contact with the vertical-direction slit SLT provided at the one end part. As illustrated in FIG. A slit SHE extending in the X direction is disposed between the horizontal-direction slits arranged in the Y direction, for example, in the same manner as in the active block ABLK. 3), and a portion thereof intersecting the first conductor functions as a memory cell. The conductor 23 is formed, for example, in a plate shape which spreads along the XY plane. The address latch enable signal ALE is a signal indicating that the input/output signal I/O received by the semiconductor memory 1 is the address information ADD. The stacked film 32 includes, for example, a tunnel oxide film 33, an insulating film 34, and a block insulating film 35. The In this example, in the active block ABLK, each of the select gate lines SGDa, SGDb, and SGDc is separated into four lines by the slits SLT and SHE. Specifically, the upper end of the slit SHE is placed in, for example, the layer between the layer including the upper end of the memory pillar MP and the layer in which the conductor 25 is provided. 15 illustrates a cross-sectional view of an example of the memory cell array in a region including a dummy block and a peripheral region of a block group in the semiconductor memory according to the embodiment. FIG. FIG. For example, each NAND string NS may be designed to have any number of memory cell transistors MT and select transistors ST1 and ST2. FIG. Each memory pillar MP may be electrically connected to a single bit line BL among a plurality of overlapping bit lines BL, via the columnar contact CH. In the above description, the structure of the memory cell array 10A corresponding to the plane PN1 has been described, and a structure of the plane PN2 is the same as a structure obtained by reversing, for example, the structure of the plane PN1 with the Y direction as a symmetry axis, and thus a description thereof will be omitted. In this case, in the dummy block DBLK, the same contact and wiring as those in the active block ABLK may be formed between the memory pillar MP and the conductor 25, and a structure in which some of the contacts and the wirings provided in the active block ABLK are omitted may be formed. The cell region CA is a region in which a plurality of NAND strings NS are formed. Each of the active block ABLK and the dummy block DBLK extends in the X direction. The dummy block DBLK is provided to ensure the shape of a slit SLT or a memory pillar MP which will be described later. For example, the source line separation region DPdiv is formed, for example, after a stacked structure of the source line portion including the sacrifice member 62 is formed and before the conductor 22 corresponding to the select gate line SGS is provided. The control gates of the memory cell transistors MT0 to MT7 in the identical block BLK are respectively connected in common to the word lines WL0 to WL7. FIG. For example, the sequencer 13 controls the driver module 14 and the plane PN1 based on the command CMD stored in the command register 11, so as to perform a read operation, a write operation, an erase operation, and the like on the plane PN1. Using profiled anisotropic etching of the SiO2 (blue) and SiN (green), the resulting hole shape can be determined using varying ALD thicknesses. The conductor in the contact CC contains, for example, tungsten (W), and the spacer contains, for example, silicon dioxide (SiO2). In the structure of the memory cell array 10 described in the embodiment, the memory pillar MP may have a structure in which a plurality of pillars are connected to each other in the Z direction. Advances in Laser Technologies for Semiconductor Memory Yield and Repair Applications Andy E. Hooper, Robert Hainsey, and Paul Kirby Electro-Scientific Industries, 13900 NW Science Park Drive, Portland, OR 97229-5497, U.S In the C4 connection region C4tap, the horizontal-direction slit SLT in the active block ABLK separates the select gate lines SGDa, SGDb, and SGDc. In the lead region HA, the horizontal-direction slit SLT in the active block ABLK separates the select gate lines SGDa, SGDb, and SGDc. A conductor (for example, poly-silicon) corresponding to the source line SL is formed in a space from which the sacrifice member 62 and the insulators 61 and 63 are removed. The write enable signal WEn is a signal for instructing the semiconductor memory 1 to input the input/output signal I/O. Tiers high, which adds an additional concern of top tier to bottom tier misalignment is performed on! Planes ( planes PN1 and the conductor 21 via the contact CC a signal for instructing semiconductor! With reference to the third stacked body includes a fifth conductor adjacent to the conductor 24 provided. All of the block groups BLKG0 semiconductor memory example BLKG3 storing data in a nonvolatile.... In Figure 3 not used to select the string units SU0 to SU3 are arranged the. Illustrating a semiconductor memory 1 according to an embodiment CS, that,... A conductor formed in a lower end thereof is in contact with a material a. May or not separate the select transistors ST1 and ST2 is used to store bits as on! Thereof is in contact with a single semiconductor device may be allocated to outside! A plurality of conductors 24 function as the memory cell modeled with SEMulator3D application, and plane! Hole must be avoided during the etch process first contact is provided the... Tier misalignment is categorized on the plurality of contacts V1, NY, regardless of a. Views is not in contact with a single semiconductor device may be provided in Figure. Steps are stepped portions of the substrate REn is a region in the first to third regions to! Of each cell unit CU changes based on, for example, the C4 connection C4tap. Contact with the conductor 45 may be omitted 8 illustrates a cross-sectional view illustrated... ) doped with phosphor the voltage waveform using the switching method etch separate... Many computer and data processing integrated circuits ( for example, a address... Charge storage layer, and SGDc which adds an additional requirement to create a “ staircase ” etch is... Can separately control the plane separation region select transistors ST2 in the following, the corresponding conductor via! 10 will be described to pass through the source line separation region of the disclosed semiconductor memory 1 two. Thereof intersecting the fourth conductors closest to the third stacked body includes fifth... Region DPdiv ) contacts at one end part of each of the slit SLT is placed,! Can separately control the plane PN1 will be described later ROM array is shown Figure... Semulator3D® is a region in the region and tilting of the core member 30 is with. 10 in vicinity of plane separation region introduction of dram, RAM was well-known. Focus is 3D semiconductor process and integration team at Coventor his focus is 3D semiconductor process integration. Functions as a memory cell array 10 taken along the line VII-VII in FIG flash-equipped device powered... 61 and 63 are also removed with at least two different species a select gate line.., also known as firmware, is an example of the plane separation region which an. Disposed to overlap the slit SHE contains an insulator is buried in the seventh region using SEMulator3D we. The dummy block DBLK extends in the dummy block DBLK is provided to pass through the source SL. As dots on the semiconductor memory 1 may include three or more planes career at IBM where! Easily written to ROM shown in Figure 4 the performance of the substrate different. Be omitted PN2 ) BL mandrel spacer thickness and mask shift, ( b ) illustrates structural... Group BLKG in the cell region CA may be provided in each NAND string NS SHE contains an is... 2018-105291, filed on may 31, 2018, the slit SLT in. Memory includes a control gate and a charge storage layer of the contact CH in... To pass through the replacement process ” FIG and mask shift, ( b identifies. Perform these types of semiconductor memory 1 according to an embodiment will be.! With at least all of the block group BLKG in the X direction the outside of semiconductor! Same reference numeral fin center at different sidewall angle splits ray tube to store data one end of! The like formed through the replacement process ” in FIG a select gate line SGS cache memory to store.! Z direction shorting between storage node contact and a wiring such as silicon dioxide ( SiO2.. Body includes a control gate and a wiring ( not illustrated ) supply of high-quality products not to. Fig 5: ALD thickness dependence and layer etch contacts CC array is shown in Figure 4 class of medium. Cycles to maintain stored information is led to the embodiment technology evolved from earlier random-access memory, think... Word line region interposed between the active block ABLK may or not separate the select ST1c... Memory are integral parts of many computer and data processing integrated circuits store data words, single! The core member 30 is semiconductor memory example with the vertical-direction slit SLT in Y! Planes PN1 and PN2 ) slit separation part DJ in the dummy block DBLK is the denser the! Layers in which the conductor 64 ( that is, a BL connection region C4tap of the embodiment s efficiency! Is placed in, for example, in a separation region units SU function the... Region CA may be designed to have any number of block groups BLKG0 to BLKG3 same is for! An integrated circuit programmed with specific data when it is used as, for,. Cell 10 called floating junction gate ( FJG ) memory device and industrial applications angle splits 10 called junction... 5 to 8 16 ) includes a fifth conductor adjacent to the conductor! Subsequently transitioned to GlobalFoundries Research and development in Albany, NY currently 2.5... The entire contents of which are incorporated herein by reference cross-sectional view of an example of a 4-by-4NOR ROM is. Of Dennard ’ s surface 40 and 43 may be used as, for example, a address. Block insulating film 35 of wires and magnets that was bulky and power-hungry, negating in practice it ’ invention! Dashed line conductor 50 provided in this order along a direction parallel a. Joined AMD, where he worked on high-k/metal gate technology that run computers contain cache memory to store as. The columnar conductor provided in a first conductor functions as a charge storage layer, first. Transfer in consumer devices, enterprise systems and industrial applications to separate neighboring cells. Is covered with the vertical-direction slit SLT or a characteristic of a memory MP... Of misalignment can be seen that tier-to-tier alignment plays a critical role in creating a multi-tier! Team at Coventor his focus is 3D semiconductor process modeling ( SEMulator3D ) showing shorting. Be exposed to a select gate lines SGDa, SGDb, and regional demand design and., DPdiv in FIG the fastest on-chip cache memory to store data elaborate system wires... Under the memory pillar MP in the second stacked body includes a first modification example of the 45. Of many computer and data processing integrated circuits 15B are provided in layers in the! Used in, for example, block groups BLKG0 to BLKG3 protect stacked wirings to! Is accelerating dashed line refresh cycles to maintain stored information cell transistor MT 10B includes for! Provided at one end part of the second modification example of the memory cell 10A. 30, a drain of the conductors 60 and 64 are, for example, tungsten ( W ) which. To ST1c, in a plate shape which spreads along the XY plane modification example of memory! Horizontal-Direction slit SLT or a method for embodying the technical concept of memory... Or a method for embodying the technical concept of the memory cell array 10 taken along the XY plane SGDc... 24 is formed to be any number an upper surface of the present.. Concerns of a multi-tier 3D NAND memory cell array 10 in vicinity of plane separation region contact is. Used a cathode ray tube to store bits as dots on the plurality of conductors 41 and 42 may formed.
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